SK Hynix Delays Hybrid Bonding for HBM4E Memory Chips
SK Hynix will not use hybrid bonding for its HBM4E memory chips. The company will keep its current MR-MUF process until HBM5 arrives. This matters because it shows a hard physical limit on today's AI memory, the same memory that could later shrink into wearables and smart glasses.
What actually happened
According to Tom's Hardware, SK Hynix confirmed hybrid bonding will not be ready for HBM4E memory. The company will extend its MR-MUF bonding method through Nvidia's Rubin AI chip platform instead. The limit is physical. HBM memory cubes cannot exceed 775 microns in total thickness, the same thickness as one standard 300mm logic wafer, per the report. SK Hynix now plans to bring hybrid bonding into its next HBM5 generation, not HBM4E. No release date for HBM5 or its hybrid bonding debut was given in the report.
How we got here
HBM chips stack several memory dies to give AI processors more bandwidth. SK Hynix currently bonds these stacks with MR-MUF, a method proven across earlier HBM generations. Industry expectations pointed to hybrid bonding arriving with HBM4E, the memory feeding Nvidia's coming Rubin platform. The 775-micron ceiling changed that plan. SK Hynix will carry MR-MUF through the entire HBM4E and Rubin cycle, pushing hybrid bonding back to HBM5. This is the first public sign that a packaging limit, not chip design, now sets the pace for AI memory upgrades.
Why this matters for you
For everyday crypto wallet users, this delay does not change anything today. Your wallet app, hardware key, or bonuz smart glasses roadmap still runs on existing chips. But it does set a slower clock for how fast AI hardware, including future wearables, can gain memory density. Builders working on AR glasses and edge AI devices should expect denser, faster memory later than earlier hoped, since hybrid bonding waits for HBM5. Investors tracking memory suppliers should read this as a timing shift, not a technology failure. The bottleneck is physical, not financial.
The bigger question
If a wafer-thickness limit, not manufacturing skill, now caps how much memory a chip can hold, how long can simple stacking keep pace with AI's growing appetite for compute? The same 775-micron ceiling applies to every company chasing denser memory, from data-center GPUs today to the compact AI chips that future smart glasses and wearables will eventually need.
What to watch
Watch for SK Hynix's HBM4E shipment schedule alongside Nvidia's Rubin platform launch. No official dates have been announced. Also watch for any update on HBM5 hybrid bonding timing, and matching statements from Samsung and Micron. Those signals will show whether the 775-micron limit becomes an industry-wide standard, something worth tracking for anyone following the chips behind future bonuz-compatible devices.
